Dr. Saikat Chatterjee

is working from home. 🏡

Angestellt, Staff Design Engineer, Socionext Europe GmbH

Munich, Deutschland

Über mich

Driven professional with 14+ years of experience, passionate about fostering talent growth. Seeking a position to utilize my skills and extensive industry knowledge while mentoring and developing the next generation of leaders.

Fähigkeiten und Kenntnisse

IC Design
Verification
Integrated circuit layout
Design
Research and Development
Architecture
ASIC
Engineering
Hardware
Leadership
Analytical skills
Commitment
Intercultural competence
Conceptual thinking

Werdegang

Berufserfahrung von Saikat Chatterjee

  • Bis heute 8 Monate, seit Nov. 2023

    Staff Design Engineer

    Socionext Europe GmbH

  • 1 Jahr und 6 Monate, Mai 2022 - Okt. 2023

    Senior Engineer

    Socionext Europe GmbH

  • 1 Jahr und 3 Monate, Feb. 2021 - Apr. 2022

    AI/ML Engineer

    IMEC vzw

  • 2 Jahre, Feb. 2019 - Jan. 2021

    Research Scientist

    Fraunhofer IIS
  • 8 Monate, Juni 2018 - Jan. 2019

    ASIC/FPGA Development Engineer

    Nokia Bell Labs

    Design and verification of RTL using VHDL, Systemverilog and formal verification of OTN modules in an Industry project for 8 months

  • 3 Jahre und 8 Monate, Okt. 2014 - Mai 2018

    Doctoral Student

    CITEC

    Research and development of a subthreshold operation compatible standard cell library and design of a system operating in subthreshold voltage synthesizable with the same standard cell library.

  • 1 Jahr und 6 Monate, Juli 2012 - Dez. 2013

    Senior Engineer

    Qualcomm

    Leading a verification team with the responsibility of verification of ARM trustzone implementation in Wireless SoCs

  • 1 Jahr und 1 Monat, Juni 2011 - Juni 2012

    Design Verification Engineer II

    Mirafra Technologies

    Design and verification at module level and top level as well at the client location

  • 1 Jahr und 7 Monate, Nov. 2009 - Mai 2011

    Design Verification Engineer I

    Avago Technologies(formerly LSI)

    Design and verification at module level

Ausbildung von Saikat Chatterjee

  • 4 Jahre und 8 Monate, Okt. 2014 - Mai 2019

    Intelligent Systems

    Universität Bielefeld

    Standard Cell Library Design, RTL design in VHDL, Optimization of circuit performance(MATLAB)

  • 2 Jahre und 4 Monate, Juli 2007 - Okt. 2009

    Instrumentation

    Indian Institute of Science

    Circuit Design, Layout Design, Digital VLSI

  • 3 Jahre und 11 Monate, Juni 2002 - Apr. 2006

    Electronics and Instrumentation

    Jadavpur University

Sprachen

  • Deutsch

    Gut

  • Englisch

    Muttersprache

Interessen

Photography
Music
Swimming (sport)

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