Amena Farhat
Angestellt, DFT Engineer, Qualcomm India
Abschluss: master's, Dr Ambedkar institute of technology Bangalore
Über mich
TRAINED IN DFT With 1.8 years of Experience DFT [design for testability] MBIST . (Synopsys SMS tetramax, VCS tool, Verdi mentor graphics) scan insertion, scan insertion with compression, boundary scan (JTAG), ATPG and MBIST professional project: Falcon Design with scan chain count 10 and scan insertion with compression ratio 50. Tools used: - Scan Insertion - DFT Compiler - Scan Insertion With Compression - DFT Compiler - Boundary Scan - BSD Compiler - Scan ATPG - TetraMAX - Simulation - VCS - MBIST - LV, SMS [ Implementation, verification and simulation ] Training included projects w.r.t Scan Insertion, Scan Insertion with Compression, ATPG Pattern Generation and Simulation along with analyzing and fixing DRC violations using Synopsys Tools
Werdegang
Berufserfahrung von Amena Farhat
Bis heute 2 Jahre und 6 Monate, seit Jan. 2022
DFT Engineer
Qualcomm India
ATPG SCAN insertion MBIST
Bis heute 2 Jahre und 9 Monate, seit Okt. 2021
DFT ENGINEER 1
Mirafra software technologies
TRAINED IN DFT With 1.8 years of Experience DFT [design for testability] MBIST . (Synopsys SMS tetramax, VCS tool, Verdi mentor graphics) scan insertion, scan insertion with compression, boundary scan (JTAG), ATPG and MBIST Tools used: - Scan Insertion - DFT Compiler - Scan Insertion With Compression - DFT Compiler - Boundary Scan - BSD Compiler - Scan ATPG - TetraMAX - Simulation - VCS - MBIST - LV, SMS [ Implementation, verification and simulation ]
Ausbildung von Amena Farhat
2 Jahre und 3 Monate, Okt. 2018 - Dez. 2020
VLSI design and embedded systems
Dr Ambedkar institute of technology Bangalore
4 Jahre und 1 Monat, Aug. 2014 - Aug. 2018
Electronics
SECAB Institute of Engineering & Technology